1. Field of the Invention
The present disclosure relates to a phase detecting method, a phase detector, and a related clock-and-data recovery device, and more particularly, to a phase detecting method, a phase detector, and a related clock-and-data recovery device for utilizing two clock signals to sample the data input signal(s) for two times.
2. Description of the Prior Art
A phase detector is one of the most important device in signal processing systems, and has been widely used in numerous different applications, such as communication devices, server controllers, and phase lock loops (PLLs).
Generally speaking, the phase detector usually utilizes a plurality of clock signals to sample the input data signal(s). However, there is usually a phase shift existed between the plurality of clock signals, respectively. For example, there is a phase shift of 90 degrees existed between a clock signal CK0 and a clock signal CK90. For this reason, when the plurality of clock signals are adopted to sample the same input data signal, the problems of phase errors existed between two sampled data may be occurred, which may cause errors on phase detections. Hence, how to prevent the problems resulted from the phase errors become one of the important topics in this field.